Bus controller for transferring data

ABSTRACT

A host controller can be used in transferring data over a USB bus communication system in frames and micro-frames. Each data transfer is described by a packet transfer descriptor, and a packet transfer descriptor for a data transfer includes a bit map, such that data is transferred according to the packet transfer descriptor only during those micro-frames of a frame which correspond to bits of the bit map for which the bit value has been set to an active value.

This invention relates to a bus controller, and in particular to adevice which can be included in electronic equipment in order to controlthe transfer of data to and from other electronic equipment using anexternal bus.

It is becoming common for electronic equipment to be provided withinterfaces allowing for the transmission of data using a UniversalSerial Bus (USB).

When items of electronic equipment are interconnected using the USBsystem, one item of equipment is designated as the USB Host, while theother items are designated as USB Devices. It is the USB Host which isresponsible for initiating and scheduling communications over the USB.For example, the USB Host may be a personal computer (PC), and it may beconnected to various USB Devices, such as a printer, a digital cameraand a personal digital assistant (PDA).

However, it is also possible to use a USB connection to connect, forexample, a camera directly to a printer without requiring connectionthrough a PC. In order to be able to function as a USB Host, an item ofequipment, which may be the camera in this example, must be providedwith the required functionality, and the present invention relates moreparticularly to a device, in the form of an integrated circuit, whichcan be included in an item of equipment, in order to provide it withthis functionality. However, it will be appreciated that the item ofequipment has other functions, and its USB interconnectivity is only asmall part of its functionality. Moreover, it is desirable to be able toinclude the device into items of equipment, in order to provide themwith the ability to act as a USB Host, without requiring those items ofequipment to have especially powerful processors.

It is therefore desirable for the device to be able to operate with thesmallest possible dependence on the central processing unit (CPU) of theitem of equipment in which it is to be incorporated. For example, thedevice preferably operates as a slave in the bus system of the item ofequipment, allowing the CPU to remain as the bus master. Further, it isdesirable for the device to place the smallest possible processingburden on the CPU, and in particular to minimize the number of interruptrequests to the CPU. Further, the device should not depend on the CPUusing any particular operating system, so that the device can beincorporated in the widest possible range of the items of equipment.

It is known to provide a USB host controller in which transfer-basedtransfer descriptors are used to define the USB transactions.

According to the present invention, there is provided a host controller,in which, for each transfer descriptor, there is provided a series ofbits, with each bit corresponding to a sub-frame in a frame, such thatdata is transferred only during sub-frames in which the correspondingbit is set to an active value.

In the Figures:

FIG. 1 is a block schematic diagram of an item of electronic equipment,incorporating a host controller in accordance with the presentinvention.

FIG. 2 is a block schematic diagram of a host controller in accordancewith the present invention.

FIG. 3 is an illustration showing the structure of software in the hostcontroller of FIG. 2.

FIGS. 4 and 5 are timing diagrams, illustrating the format of USB datatransmitted from the host controller.

FIG. 6 gives an overview of the isochronous high speed packet transferdescriptor according to the invention.

FIGS. 7 and 8 are timing diagrams, illustrating the format of USB datatransmitted from the host controller.

FIG. 9 shows how a polling rate for an endpoint can be varied.

FIG. 10 gives an overview of the interrupt high speed packet transferdescriptor according to the invention.

FIGS. 11 and 12 are timing diagrams, illustrating the format of USB datatransmitted from the host controller.

FIG. 13 gives an overview of the bulk high speed packet transferdescriptor according to the invention.

FIG. 1 is a block schematic diagram of the relevant parts of an item 10of electronic equipment, operating as a USB host. The invention isparticularly applicable to devices such as cameras, set-top boxes,mobile phones, or PDAs, in which the functional limitations of themicroprocessor and the system memory are more relevant, rather than inpersonal computers (PCs). However, the invention is applicable to anydevice which can operate as a USB host.

It will be apparent that the device 10 will have many features, whichare not shown in FIG. 1, since they are not relevant to an understandingof the present invention.

The device 10 has a host microprocessor (CPU) 20, which includes aprocessor core. The CPU 20 is connected to a system memory 30 by meansof a peripheral bus 32.

A host controller 40 is also connected to the host microprocessor 20 andthe system memory 30, by means of the peripheral bus, or memory bus, 32.The host controller 40 has an interface for a USB bus 42, through whichit can be connected to multiple USB devices. In this illustratedembodiment, the host controller 40 is a USB 2.0 host controller, andfeatures of the host controller not described herein may be as specifiedin the USB 2.0 specification.

As is conventional, the host controller 40 is adapted to retrieve datawhich is prepared by the processor 20 in a suitable format, and totransmit the data over the bus interface. In USB communications, thereare two categories of data transfer, namely asynchronous transfer andperiodic transfer. Control and bulk data are transmitted usingasynchronous transfer, and isochronous and interrupt data aretransmitted using periodic transfer. A Queue Transaction Descriptor(qTD) data structure is used for asynchronous transfer, and anIsochronous Transaction Descriptor (iTD) data structure is used forperiodic transfer.

The processor 20 prepares the data in the appropriate structure, andstores it in the system memory 30, and the host controller 40 must thenretrieve the data from the system memory 30.

FIG. 2 shows in more detail the structure of the embedded USB hostcontroller 40.

As mentioned above, the host controller 40 has a connection for thememory bus 32, which is connected to an interface 44, containing aMemory Management Unit, a Slave DMA Controller, an interrupt controlunit, and hardware configuration registers. The interface 44 also has aconnection 46 for control and interrupt signals, and registers 48 whichsupport the RAM structure and the operational registers of the hostcontroller 40.

The interface 44 is connected to the on-chip RAM 50 of the hostcontroller, which in this preferred embodiment is a dual port RAM,allowing data to be written to and read from the memory simultaneously,but could equivalently be a single port RAM with an appropriate arbiter.The memory 50 is connected to the host controller logic unit 52, whichalso contains an interface for the USB bus 42. Control signals can besent from the registers 48 to the logic unit 52 on an internal bus 54.

FIG. 3 is a schematic diagram showing in part the software operating onthe host controller 40, in order to illustrate the method of operationof the device according to the invention.

The host controller 40 runs USB driver software 80 and USB Enhanced HostController Interface software 82, which are generally conventional.

The host controller 40 also runs USB EHCI interface software 84, whichprepares a list of transfer-based transfer descriptors for everyendpoint to which data is to be transmitted.

The EHCI interface software 84 is written such that it uses theparameters which are generated by the EHCI host stack 82 for theexisting periodic and asynchronous headers, and can be used for alldifferent forms of USB transfer, in particular high speed USB transfer,such as high speed isochronous, bulk, interrupt and control andstart/stop split transactions.

The host microprocessor 20 writes the transfer-based transferdescriptors into the RAM 50 of the host controller 40 through theperipheral bus 32, without the host controller 40 requiring to masterthe bus 32. In other words, the host controller 40 acts only as a slave.The transfer-based transfer descriptors can then be memory-mapped intothe RAM 50 of the host controller 40.

Advantageously, the built-in memory 50 of the host controller 40 ismapped in the host microprocessor 20, improving the ease with whichtransactions can be scheduled from the host microprocessor 20.

The use of a dual-port RAM 50 means that, while one transfer-basedtransfer descriptor is being executed by the host controller 40, thehost microprocessor 20 can be writing data into another block space.

FIG. 4 illustrates the format of one USB frame, divided into multiplemicro-frames, in which data is transmitted from the host controller 40over the USB bus 42. As is conventional, multiple transactions,including transactions of different transfer types, may be sent withinone micro-frame. Again, as is conventional, high speed isochronoustransfer is always first, followed by high speed interrupt transfer, andfull speed and low speed Start Split and Complete Split transfers, withhigh speed bulk data occupying the remaining time in the micro-frame.FIG. 4 shows the way in which multiple high speed isochronoustransactions may be sent to one or more endpoints.

Specifically, in FIG. 4, two high speed isochronous transfer descriptorsare being processed in a single millisecond from 1 ms-2 ms. Thisrepresents a frame, which is made up of eight micro-frames, beginning atuSOF0, uSOF1, . . . , uSOF7 respectively. FIG. 4 also shows the formatsof the corresponding packet transfer descriptors, PTD1, PTD2, relatingto different endpoints (endpt1, endpt2) for respective IN or OUTtransactions. Each of the packet transfer descriptors, PTD1, PTD2contains a series of eight bits, labelled usof(7-0), and these bits maytake an active value (that is, a “1”) or a non-active value, (that is, a“0”). Payload data is then transferred when all of the parameters of thepacket transfer descriptors are met, namely during the appropriate Frame#, and during the micro-frames when the usof bit is high.

Thus, in FIG. 4, payload data (HSISO1) relating to the packet transferdescriptor PTD1 is sent during all eight micro-frames, while payloaddata (HSISO2) relating to the packet transfer descriptor PTD2 is sentonly during the four micro-frames beginning at uSOF0, uSOF2, uSOF4 anduSOF6, for which the respective usof bits are set high.

When the packet transfer descriptor parameter multi takes the value 1,only 1 transaction of Max Packet Data Size is sent out for each endpointin each micro-frame.

When the payload data relating to a packet transfer descriptor hasfinished, a hardware interrupt is sent to the CPU 20. These IRQs can beset active when the individual packet transfer descriptors are complete,as shown at 140 in FIG. 4, or only when both packet transfer descriptorsare complete, as shown at 142 in FIG. 4.

FIG. 5, shows a multi-millisecond transfer situation, in which four highspeed isochronous transfer descriptors are being processed over a periodfrom 1 ms-5 ms. This represents four frames, each made up of eightmicro-frames, with only two micro-frames in each frame, being shown, forclarity. FIG. 5 also shows the formats of the corresponding packettransfer descriptors, PTD1-PTD8. In this case, each of the eight packettransfer descriptors, PTD1-PTD8 relates to the same endpoint (endpt1).Also, each of the packet transfer descriptors, PTD1-PTD8 contains aseries of eight bits, labelled usof(7-0), and these bits may take anactive value (that is, a “1”) or a non-active value, (that is, a “0”).Payload data is then transferred when all of the parameters of thepacket transfer descriptors are met, namely during the appropriate Frame#, and during the micro-frames when the usof bit is high.

Thus, in FIG. 5, payload data (HSISO1) relating to the packet transferdescriptor PTD1 is sent during all eight micro-frames of frame #01,while payload data (HSISO1) relating to the packet transfer descriptorPTD2 is sent during all eight micro-frames of frame #02, and so on.Thus, defining multiple isochronous packet transfer descriptors allowsmulti-millisecond transactions.

Further, in this case, the packet transfer descriptor parameter multitakes the value 3, and so three transactions of Max Packet Data Size aresent out for each endpoint in each micro-frame.

Thus, the packet transfer descriptors PTD1-PTD4 are processed over aperiod from 1 ms-5 ms. While the packet transfer descriptors PTD 1-PTD4are being sent, new packet transfer descriptors PTD5-PTD8 for the next 4ms can be prepared. A SKIP bitmap can be set active until all packettransfer descriptors PTD5-PTD8 are prepared, and then the bitmap can beunskipped.

An IRQ only happens to indicate that the first 4 ms are completed, andthen the data for IN Token can be read back.

There is therefore a continuous flow of USB data at the maximum USB datarate of 24 KB/ms (that is, 1024 bytes per transaction ×3 transactions ineach micro-frames ×8 micro-frames per millisecond).

FIG. 6 gives an overview of the isochronous high speed packet transferdescriptor according to the invention.

FIG. 7 shows a situation in which two high speed interrupt transferdescriptors are being processed over a two millisecond period from 1ms-3 ms. Each millisecond represents a frame, which is made up of eightmicro-frames, beginning at uSOF0, uSOF1, . . . , uSOF7 respectively.FIG. 7 also shows the formats of the corresponding packet transferdescriptors, PTD1, PTD2, relating to different endpoints (endpt1,endpt2). Each of the packet transfer descriptors, PTD1, PTD2 contains aseries of eight bits, labelled usof(7-0), and these bits may take anactive value (that is, a “1”) or a non-active value, (that is, a “0”).Payload data is then transferred during the micro-frames when the usofbit is high.

Thus, in FIG. 7, payload data (HSINT1) relating to the packet transferdescriptor PTD1 is sent during the four micro-frames beginning at uSOF1,uSOF3, uSOF5 and uSOF7, for which the respective usof bits are set high,while payload data (HSINT2) relating to the packet transfer descriptorPTD2 is sent only during the four micro-frames beginning at uSOF0,uSOF2, uSOF4 and uSOF6, for which the respective usof bits are set high.

Each of the packet transfer descriptors, PTD1, PTD2 also indicates thesize of the payload (PL), and it will be noted that the payload of PTD2is double the size of the payload of PTD1. Therefore, while PTD1 iscompleted during the first millisecond, payload data (HSINT2) relatingto the packet transfer descriptor PTD2 is also sent during the fourmicro-frames beginning at uSOF0, uSOF2, uSOF4 and uSOF6 of themillisecond from 2 ms-3 ms.

When the payload data relating to a packet transfer descriptor hasfinished, a hardware interrupt is sent to the CPU 20. These IRQs can beset active when the individual packet transfer descriptors are complete,as shown at 170 in FIG. 7, or only when both packet transfer descriptorsare complete, as shown at 172 in FIG. 4.

FIG. 8 shows a multi-millisecond transfer situation, in which four highspeed interrupt transfer descriptors are being processed over a periodfrom 2 ms-23 ms. As before, each millisecond represents a frame, eachframe being made up of eight micro-frames.

FIG. 8 also shows the formats of the corresponding packet transferdescriptors, PTD1-PTD4. In this case, each of the four packet transferdescriptors, PTD1-PTD4 relates to a respective different endpoint(endpt1, endpt2, endpt3, endpt4). Also, each of the packet transferdescriptors, PTD1-PTD4 contains a series of eight bits, labelledusof(7-0), and these bits may take an active value (that is, a “1” or anon-active value, (that is, a “0”). Payload data is then transferredonly during the appropriate Frame # specified in the packet transferdescriptor, and during the micro-frames when the usof bit is high.

The packet transfer descriptor also specifies the payload (PL) size, themaximum packet size (MPS) and the polling rate for the transfer. Thus,the polling rate can be varied as required, between 1 micro-frame and 32frames in this example. FIG. 9 is a table showing the available valuesof the polling rate. When two endpoints have the same polling rate,their transactions can be distributed on two different frames. This canbe done by hardware activating the transactions based on the last 2 bitsof the frame numbers.

FIG. 8 shows how this works in practice. For example, data intended forendpoint 3, described by packet transfer descriptor PTD3, is NAKed inthe frame at 4 ms, and so is retransmitted in the frame at 8 ms since ithas a polling rate of 8 ms. Similarly, data intended for endpoint 4,described by packet transfer descriptor PTD4, is NAKed in the frame at 7ms, and so is retransmitted in the frame at 23 ms since it has a pollingrate of 16 ms.

FIG. 10 gives an overview of the interrupt high speed packet transferdescriptor according to the invention.

FIG. 11 illustrates the transfer mechanism for bulk transfer of data.Thus, in one frame, during the period of the first four micro-frames,beginning at uSOF0-uSOF3, data according to a first packet transferdescriptor PTD1 is being delivered, while data according to a secondpacket transfer descriptor PTD2 is being prepared, as shown at 190 inFIG. 11. During the period of the second four micro-frames, beginning atuSOF4-uSOF7, data according to the second packet transfer descriptorPTD2 is being delivered, while data according to the first packettransfer descriptor PTD1 is being prepared, as shown at 192 in FIG. 11.This allows a high data transfer rate to an endpoint, while requiringonly two interrupts per millisecond.

As is conventional, bulk data is sent in a micro-frame only after theisochronous and interrupt data has been sent. FIG. 12 shows a situationin which four high speed interrupt transfer descriptors are beingprocessed over several micro-frames, but only after the isochronous data(HSISO) and interrupt data (HSINT) has been sent in that micro-frame.

FIG. 12 also shows the formats of the corresponding packet transferdescriptors, PTD1-PTD4. In this case, each of the four packet transferdescriptors, PTD1-PTD4 relates to a respective different endpoint(endpt1, endpt2, endpt3, endpt4). The parameter multi indicates thenumber of bulk data packets that can be transferred according to apacket transfer descriptor before data is transferred according to anyother packet transfer descriptor in any micro-frame. Thus, the firstpacket transfer descriptor PTD1 has the value 3 for the parameter multi,and so three packets are transferred in the micro-frame beginning at 1ms, before data is transferred according to any other packet transferdescriptor. In this case, there was no isochronous or interrupt data,and so the cycle of bulk data transfer can be repeated in themicro-frame.

However, it will be noted that, in the micro-frame beginning at uSOF2,there was a large amount of isochronous data, and so the cycle of bulkdata transfer could not be completed within the micro-frame.

FIG. 13 gives an overview of the high speed packet transfer descriptorfor bulk and control endpoints, according to the invention.

1. A host controller, for use in transferring data over a buscommunication system in frames and micro-frames, in which each datatransfer is described by a packet transfer descriptor, wherein a packettransfer descriptor for a data transfer includes a bit map, such thatdata is transferred according to the packet transfer descriptor onlyduring those micro-frames of a frame which correspond to bits of the bitmap for which the bit value has been set to an active value.
 2. A hostcontroller as claimed in claim 1, for use in transferring data over saidbus communication system either to isochronous endpoints or to interruptendpoints, wherein packet transfer descriptors for data transfer both toisochronous endpoints and to interrupt endpoints include said bit map.3. A host controller as claimed in claim 2, wherein the packet transferdescriptor for data transfer to interrupt endpoints further specifies avariable polling rate.
 4. A host controller as claimed claim 1, for usein a bus communication device comprising a host microprocessor and asystem memory, the host controller further comprising: a first interfacefor connection to a memory bus which connects the host microprocessorand the system memory, such that the host controller is adapted to actonly as a slave on the memory bus; and a second interface, forconnection to the bus communication system.
 5. A method of operation ofa host controller, for transferring data over a bus communication systemin frames and micro-frames, the method comprising: describing each datatransfer by a packet transfer descriptor, wherein a packet transferdescriptor for a data transfer includes a bit map, and wherein themethod comprises transferring data according to the packet transferdescriptor only during those micro-frames of a frame which correspond tobits of the bit map for which the bit value has been set to an activevalue.
 6. A method as claimed in claim 5, for transferring data oversaid bus communication system either to isochronous endpoints or tointerrupt endpoints, wherein the packet transfer descriptors for datatransfer both to isochronous endpoints and to interrupt endpointsinclude said bit map.
 7. A method as claimed in claim 6, wherein thepacket transfer descriptor for data transfer to interrupt endpointsfurther specifies a variable polling rate.